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M378B5773CH0 Datasheet, PDF (17/37 Pages) Samsung semiconductor – 240pin Unbuffered DIMM based on 2Gb C-die
◁
Unbuffered DIMM
datasheet
12.3 AC and DC Logic Input Levels for Differential Signals
12.3.1 Differential Signals Definition
Rev. 1.21
DDR3 SDRAM
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
tDVAC
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC
12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
Symbol
VIHdiff
VILdiff
VIHdiff(AC)
VILdiff(AC)
Parameter
differential input high
differential input low
differential input high ac
differential input low ac
DDR3-800/1066/1333/1600
min
max
+0.2
NOTE 3
NOTE 3
-0.2
2 x (VIH(AC) - VREF)
NOTE 3
NOTE 3
2 x (VIL(AC) - VREF)
unit
NOTE
V
1
V
1
V
2
V
2
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-
ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
[ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
min
max
> 4.0
75
-
4.0
57
-
3.0
50
-
2.0
38
-
1.8
34
-
1.6
29
-
1.4
22
-
1.2
13
-
1.0
0
-
< 1.0
0
-
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
min
max
175
-
170
-
167
-
163
-
162
-
161
-
159
-
155
-
150
-
150
-
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