K9F6408U0C Datasheet, PDF (17/30 Pages) Samsung semiconductor – 8M x 8 Bit NAND Flash Memory

K9F6408U0C
FLASH MEMORY
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-
ing would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE
CE don’t-care
WE
ALE
I/O0~7
CE
80h Start Add.(3Cycle)
tCS
tCH
Data Input
CE
Data Input
10h
tCEA
tWP
WE
RE
I/O0~7
tREA
out
Timing requirements : If CE is is exerted high during data-loading,
tCS must be minimum 10ns and tWC must be increased accordingly.
Timing requirements : If CE is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 45ns.
Figure 4. Read Operation with CE don’t-care.
CLE
CE
On K9F6408U0C_T,Q or K9F6408U0C_V,F
CE must be held
low during tR
CE don’t-care
RE
ALE
R/B
WE
I/O0~7
tR
00h Start Add.(3Cycle)
Data Output(sequential)
17