K7A323630C Datasheet, PDF (17/19 Pages) Samsung semiconductor – 1Mx36 and 2Mx18 Synchronous SRAM

K7A323630C
K7A321830C
Preliminary
1Mx36 & 2Mx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 512Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 512K depth to 1M depth without extra logic.
Data
Address
A[0:19]
A[19]
A[0:18]
I/O[0:71]
A[19] A[0:18]
CLK
Microprocessor
ADS
Address
CLK
Cache
Controller
Address Data
CS2
CS2
CLK
ADSC
WEx
OE
512Kx36
SPB
SRAM
(Bank 0)
CS1
ADV ADSP
Address Data
CS2
CS2
CLK
ADSC
WEx
OE
512Kx36
SPB
SRAM
(Bank 1)
CS1
ADV ADSP
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Clock
ADSP
tSS
tSH
ADDRESS ^A1
[0:n]
tWS
tWH
WRITE
tAS
tAH
A2
CS1
An+1
ADV
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
tADVS
tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
OE
Data Out
(Bank 0)
Data Out
(Bank 1)
tOE
tLZOE
Q1-1
Q1-2
Q1-3
tHZC
Q1-4
tCD
tLZC
*Notes : n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
Q2-1 Q2-2 Q2-3 Q2-4
Don′t Care Undefined
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Rev. 0.2 April 2006