S3C84BB Datasheet, PDF (162/361 Pages) Samsung semiconductor – 8-BIT CMOS

INSTRUCTION SET
S3C84BB/F84BB
CLR — Clear
CLR
dst
Operation:
dst ← "0"
The destination location is cleared to "0".
Flags:
No flags are affected.
Format:
opc
dst
Bytes
2
Cycles
4
4
Opcode
(Hex)
B0
B1
Addr Mode
dst
R
IR
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR
00H
→
Register 00H = 00H
CLR
@01H
→
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H.
In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode
to clear the 02H register value to 00H.
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