K4H280438F Datasheet, PDF (15/23 Pages) Samsung semiconductor – 128Mb F-die DDR SDRAM Specification

DDR SDRAM 128Mb F-die (x4, x8)
DDR SDRAM
AC Timming Parameters & Specifications
Parameter
B3
A2
B0
A0
Symbol ^{(DDR333@CL=2.5 (DDR266@CL=2.0 (DDR266@CL=2.5 (DDR200@CL=2.0} Unit Note
Min Max Min Max Min Max Min Max
Row cycle time
tRC
60
65
65
70
ns
Refresh row cycle time
tRFC
72
75
75
80
ns
Row active time
tRAS
42
70K
45
120K
45
120K
48
120K ns
RAS to CAS delay
tRCD
18
20
20
20
ns
Row precharge time
tRP
18
20
20
20
ns
Row active to Row active delay
tRRD
12
15
15
15
ns
Write recovery time
tWR
15
15
15
15
ns
Last data in to Read command
tWTR
1
1
1
1
tCK
Col. address to Col. address delay
tCCD
1
1
1
1
tCK
Clock cycle time
CL=2.0
7.5
12
7.5
12
10
12
10
12
ns
tCK
CL=2.5
6
12
7.5
12
7.5
12
ns
Clock high level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock low level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS-out access time from CK/CK
tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns
Output data access time from CK/CK
tAC
-0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns
Data strobe edge to ouput data edge
tDQSQ
-
0.45
-
0.5
-
0.5
-
0.6
ns 12
Read Preamble
tRPRE 0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1 tCK
Read Postamble
tRPST 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 tCK
CK to valid DQS-in
tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS-in setup time
tWPRES 0
0
0
0
ns 3
DQS-in hold time
tWPRE 0.25
0.25
0.25
0.25
tCK
DQS falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH 0.35
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL 0.35
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1 tCK
Address and Control Input setup time(fast)
tIS
0.75
0.9
0.9
1.1
ns ^i,5.7
Address and Control Input hold time(fast)
tIH
0.75
0.9
0.9
1.1
ns ^i,5.7
Address and Control Input setup time(slow)
tIS
0.8
1.0
1.0
1.1
ns ^i,
Address and Control Input hold time(slow)
tIH
0.8
1.0
1.0
1.1
ns ^i,
Data-out high impedence time from CK/CK
tHZ
+0.7
+0.75
+0.75 -0.8
+0.8 ns 1
Data-out low impedence time from CK/CK
tLZ
-0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns 1
Mode register set cycle time
tMRD
12
15
15
16
ns
DQ & DM setup time to DQS
tDS
0.45
0.5
0.5
0.6
ns j, k
DQ & DM hold time to DQS
tDH
0.45
0.5
0.5
0.6
ns _{j, k}
Control & Address input pulse width
tIPW
2.2
2.2
2.2
2.5
ns 8
DQ & DM input pulse width
tDIPW 1.75
1.75
1.75
2
ns 8
Power down exit time
tPDEX
6
7.5
7.5
10
ns
Exit self refresh to non-Read command
tXSNR
75
75
75
80
ns
Exit self refresh to read command
tXSRD 200
200
200
200
tCK
Refresh interval time
tREFI
7.8
7.8
7.8
15.6
us 4
Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67
1.5
0.67
1.5
0.67
1.5
0.67
1.5
Rev. 1.1 May. 2004