S1T8536 Datasheet, PDF (14/24 Pages) Samsung semiconductor – 2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER

S1T8536
RECEIVER FUNCTIONAL DESCRIPTION
2.4GHZ-2.5GHZ SINGLE-CHIP RF TRANSCEIVER
C1
Vout
C2
R2 R1
Vin
21
BUF OUT
22
BUF IN
Data Slicer with Sample and Hold
The data slicer is a comparator that is designed to square up the data signal. The recovered data signal from the
baseband filter output can be DC coupled to the data slicer DS-INP(Pin 20). The S1T8536’s data slicer
incorporates an sample and hold used to derive the data slicer reference voltage by means of an external
integration circuit. The sample and hold is ’ON’ during reception of the preamble data pattern, and is otherwise
‘OFF’ in TDD (Time Division Duplex) system. The external integration circuit is formed by an RC low pass circuit
placed between SHO (Pin 18) and ground.
The size of this resistor and capacitor and the nature of the data signal determine how faithfully the data slicer
shapes up the recovered signal. The time constant is short for large peak to peak voltage swings or when there is a
change in DC level at the detector output. For small signal or for continuous bits of the same polarity which drift
close to the threshold voltage, the time constant is longer.
The sample and hold is able to sink/source 3mA to/from the external integration circuit in order to minimize the
settling time. When the sample and hold is ‘OFF’ the output (SHO) is in high impedance state with extremely low
leakage current.
Following figure shows the internal block diagram.
DS INP ₂₀
DS INN ¹⁹
SHO 18
SHEN ₁₆
17 DS OUT
+1
The output of the data slicer (DS-OUT) is a CMOS compatible bitstream. However, it is recommended that an
external NPN amplifier stage be used to drive the CMOS baseband processor, in order to minimize the amount of
ground and supply currents in the S1T8536 which might desensitize the chip.
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