KM732V589L Datasheet, PDF (14/15 Pages) Samsung semiconductor – 32Kx32 Synchronous SRAM

KM732V589A/L
PRELIMINARY
32Kx32 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 32Kx32 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 32K depth to 64K depth without extra logic.
Data
Address
A[0:15]
A[15]
A[0:14]
A[15]
I/O[0:63]
A[0:14]
CLK
64-Bits
Microprocessor
Address
CLK
Cache
Controller
Address Data
CS2
CS2
CLK
ADSC
WEx
OE
32Kx32
SPB
SRAM
(Bank 0)
CS1
ADV
ADSP
Address Data
CS2
CS2
CLK
ADSC
WEx
OE
32Kx32
SPB
SRAM
(Bank 1)
CS1
ADV ADSP
ADS
* Please refer to attached timing diagram 2
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
Clock
ADSP
tSS
tSH
ADDRESS A1
[0:n]
tWS
tWH
WRITE
tAS
tAH
A2
CS1
An+1
ADV
tCSS
tCSH
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
tADVS
tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
OE
Data Out
(Bank 0)
Data Out
(Bank 1)
tOE
tLZOE
Q1-1
Q1-2
Q1-3
tHZC
Q1-4
tCD
tLZC
*NOTES n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
Q2-1
Q2-2 Q2-3 Q2-4
Don′t Care Undefined
- 14 -
May 1997
Rev 1.0