K9WAG08U1A_067 Datasheet, PDF (14/50 Pages) Samsung semiconductor – 1G x 8 Bit / 2G x 8 Bit / 4G x 8 Bit NAND Flash Memory

K9WAG08U1A
K9K8G08U0A K9NBG08U5A
FLASH MEMORY
Program / Erase Characteristics
Parameter
Program Time
Dummy Busy Time for Two-Plane Page Program
Number of Partial Program Cycles
Symbol
Min
Typ
Max
Unit
tPROG
-
200
700
µs
tDBSY
-
0.5
1
µs
Nop
-
-
4
cycles
Block Erase Time
tBERS
-
1.5
2
ms
NOTE : 1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C tempera-
ture.
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
Address to Data Loading Time
tCLS⁽¹⁾
tCLH
tCS⁽¹⁾
tCH
tWP
tALS⁽¹⁾
tALH
tDS⁽¹⁾
tDH
tWC
tWH
tADL⁽²⁾
Min
K9NBG08U5A
K9K8G08U0A
K9WAG08U1A
25
12
10
5
35
20
10
5
25
12
25
12
10
5
20
12
10
5
45
25
15
10
70
70
Max
K9NBG08U5A
K9K8G08U0A
K9WAG08U1A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
14