K7D323674C Datasheet, PDF (13/18 Pages) Samsung semiconductor – 1Mx36 & 2Mx18 SRAM

K7D323674C
K7D321874C
1Mx36 & 2Mx18 SRAM
TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES
(Burst Length=4, 2)
NOP
READ
READ
READ CONTINUE READ
CONTINUE READ
NOP
(burst of 4)
(burst of 4)
(burst of 2)
NOP
WRITE
READ
WRITE CONTINUE READ CONTINUE
(burst of 4)
(burst of 4)
1
2
3
4
5
6
7
8
9
10
11
12
K
tKHKH
K
B1
B2
tBVKH
B3
tKHBX
SA
A0
A5
A1
tAVKH
tKHAX
A2
A3
DQ QX2
Q01 Q02 Q03 Q04 Q51 Q52 Q53 Q54 Q11 Q12
tKHDX
tDVKH
D21 D22 D23 D24
Q31
tCHQZ
CQ
CQ
tKXCH ^tCHQV
tCHLZ
tCHQX _tCLQV
tKXCL
tCLQX
tCHCL tCLCH
DON’T CARE
UNDEFINED
NOTE
1. Q01 refers to output from address A. Q02 refers to output from the next internal burst address following A, etc.
2. Outputs are disabled(High-Z) one clock cycle after NOP detected or after no pending data requests are present.
3. Doing more than one Read Continue or Write Continue will cause the address to wrap around.
Rev. 1.0 August 2006
- 13