K7Q163654A Datasheet, PDF (12/17 Pages) Samsung semiconductor – 512Kx36-bit, 1Mx18-bit QDR SRAM

K7Q163654A
K7Q161854A
512Kx36 & 1Mx18 QDR^TM b4 SRAM
TIMING WAVE FORMS OF READ AND NOP
READ
tKHKH
tKLKH
K
READ
tKHKL
tKHKH
K
SA
A1
tAVKH
tKHAX
A2
tIVKH tKHIX
R
tCHQX1
Q(Data Out)
C
tKHCH
Q1-1
Q1-2 Q1-3
tCHQX
tCHQV
Q1-4
Q2-1
NOP
Q2-2
Q2-3
Q2-4
tCHQZ
C
tCHQV
Don′t Care Undefined
Note: 1. Q1-1 refers to output from address A1+0, Q1-2 refers to output from address A1+1 i.e. the next internal burst address following A1+0.
2. Outputs are disabled one cycle after a NOP.
TIMING WAVE FORMS OF WRITE AND NOP
WRITE
tKHKH
tKLKH
K
WRITE
tKHKL
K
SA
A1
tKHKH
tAVKH
tKHAX
A2
tIVKH tKHIX
W
tKHIX
NOP
D(Data In)
D1-1 D1-2 D1-3 D1-4 D2-1 D2-2 D2-3 D2-4
tDVKH
tKHDX
Don′t Care
Note: 1. D1-1 refers to input to address A1+0, D1-2 refers to input to address A1+1, i.e the next internal burst address following A1+0.
Undefined
- 12 -
July. 2002
Rev 1.0