K7Q163664B_10 Datasheet, PDF (10/17 Pages) Samsung semiconductor – 512Kx36 & 1Mx18 QDRTM b4 SRAM

K7Q163664B
K7Q161864B
Overershoot Timing
VDDQ+0.7V
VDDQ+0.35V
VDDQ
20% tKHKH(MIN)
VIL
512Kx36 & 1Mx18 QDR^TM b4 SRAM
Undershoot Timing
VIH
VSS
VSS-0.35V
VSS-0.7V
20% tKHKH(MIN)
RECOMMENDED DC OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
PARAMETER
SYMBOL
MIN
TYP
Supply Voltage
VDD
1.7
2.5
VDDQ
1.4
1.5
Reference Voltage
VREF
0.68
0.75
Ground
VSS
0
0
MAX
2.6
1.9
0.95
0
UNIT
V
V
V
V
AC TIMING CHARACTERISTICS
PARAMETER
SYMBOL
Clock
Clock Cycle Time(K, K, C, C)
Clock HIGH time (K, K, C, C)
Clock LOW time (K, K, C, C)
Clock to clock (K↑ → K↑, C↑ → C↑)
Clock to data clock (K↑ → C↑, K↑→ C↑)
Output Times
C, C High to Output Valid
C, C High to Output hold
C High to Output High-Z
C High to Output Low-Z
Setup Times
Address valid to K rising edge
Control inputs valid to K rising edge
Data-in valid to K, K rising edge
Hold Times
K rising edge to address hold
K rising edge to control inputs hold
K, K rising edge to data-in hold
tKHKH
tKHKL
tKLKH
tKHKH
tKHCH
tCHQV
tCHQX
tCHQZ
tCHQX1
tAVKH
tIVKH
tDVKH
tKHAX
tKHIX
tKHDX
-16
MIN
MAX
6.0
2.4
2.4
2.7
3.3
0.0
2.0
2.5
1.2
2.5
1.2
0.7
0.7
0.7
0.7
0.7
0.7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
v
ns
ns
NOTES
3
3
3
3
2
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control signals are R, W,BW0,BW1 and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 2.6V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 2.4V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
- 10 -
Aug. 2010
Rev 1.1