K7I643684M Datasheet, PDF (10/18 Pages) Samsung semiconductor – 72Mb DDRII SRAM Specification

K7I643684M
K7I641884M
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
Storage Temperature
Operating Temperature (Commercial / Industrial)
Storage Temperature Range Under Bias
SYMBOL
VDD
VDDQ
VIN
TSTG
TOPR
TBIAS
RATING
-0.5 to 2.9
-0.5 to VDD
-0.5 to VDD+0.3
-65 to 150
0 to 70 / -40 to 85
-10 to 85
UNIT
V
V
V
°C
°C
°C
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
OPERATING CONDITIONS (0°C ≤ TA ≤ 70°C)
PARAMETER
SYMBOL
Supply Voltage
VDD
VDDQ
Reference Voltage
VREF
MIN
MAX
UNIT
1.7
1.9
V
1.4
1.9
V
0.68
0.95
V
DC ELECTRICAL CHARACTERISTICS(VDD=1.8V ±0.1V, TA=0°C to +70°C)
PARAMETER
Input Leakage Current
Output Leakage Current
Operating Current (x36):
QDR mode
Operating Current (x18):
QDR mode
Standby Current(NOP):
QDR mode
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Input Low Voltage
Input High Voltage
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT NOTES
IIL
VDD=Max ; VIN=VSS to VDDQ
-2
+2
µA
IOL Output Disabled,
-2
+2
µA
-30
-
900
VDD=Max, IOUT=0mA
ICC
Cycle Time ≥ tKHKH Min
-25
-
-20
-
800
mA 1,4
700
-16
650
-30
-
850
VDD=Max, IOUT=0mA
ICC
Cycle Time ≥ tKHKH Min
-25
-
-20
-
750
mA 1,4
650
-16
-
600
-30
-
Device deselected, IOUT=0mA, _-25
-
ISB1 f=Max,
All Inputs≤0.2V or ≥ VDD-0.2V ^-20
-
-16
-
400
380
mA 1,5
360
340
VOH1
VDDQ/2-0.12 VDDQ/2+0.12 V
2,6
VOL1
VDDQ/2-0.12 VDDQ/2+0.12 V
2,6
VOH2 IOH=-1.0mA
VDDQ-0.2
VDDQ
V
3
VOL2 IOL=1.0mA
VSS
0.2
V
3
VIL
-0.3
VREF-0.1
V
7,8
VIH
VREF+0.1 VDDQ+0.3
V
7,9
Notes: 1. Minimum cycle. IOUT=0mA.
2. |IOH|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω. |IOL|=(VDDQ/2)/(RQ/5)±15% for 175Ω ≤ RQ ≤ 350Ω.
3. Minimum Impedance Mode when ZQ pin is connected to VDDQ.
4. Operating current is calculated with 50% read cycles and 50% write cycles.
5. Standby Current is only after all pending read and write burst operations are completed.
6. Programmable Impedance Mode.
7. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
8. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
9. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
Rev. 1.3 March 2007
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