K4S560432J Datasheet, PDF (10/15 Pages) Samsung semiconductor – 256Mb J-die SDRAM Specification

K4S560432J
K4S560832J
K4S561632J
Synchronous DRAM
12.0 DC Characteristics (x16)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
50
Operating current
(One bank active)
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
110
Precharge standby current in ^{ICC2P CKE ≤ VIL(max), tCC = 10ns}
power-down mode
ICC2PS CKE & CLK ≤ V_IL(max), tCC = ∞
Precharge standby current in
non power-down mode
ICC2N ^{CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns}
Input signals are changed one time during 20ns
ICC2NS ^{CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞}
Input signals are stable
Active standby current in
power-down mode
ICC3P CKE ≤ V_IL(max), tCC = 10ns
ICC3PS CKE & CLK ≤ V_IL(max), tCC = ∞
Active standby current in
non power-down mode
(One bank active)
ICC3N ^{CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns}
Input signals are changed one time during 20ns
ICC3NS ^{CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞}
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
ICC4
Page burst
4banks Activated.
140
tCCD = 2CLKs
Refresh current
ICC5 tRC ≥ tRC(min)
200
C
Self refresh current
ICC6 CKE ≤ 0.2V
L
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S561632J-UC
4. K4S561632J-UL
5. Unless otherwise noticed, input swing level is CMOS(V_IH/V_IL=V_DDQ/V_SSQ).
Version
60
90
2
2
15
10
5
5
28
20
120
180
3
1.5
Unit Note
75
70 mA 1
mA
mA
mA
mA
mA
110 mA 1
160 mA 2
mA 3
mA 4
10 of 15
Rev. 1.22 August 2008