M464S1724DTS Datasheet, PDF (1/11 Pages) Samsung semiconductor – 16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD

M464S1724DTS
PC133/PC100 SODIMM
M464S1724DTS SDRAM SODIMM
16Mx64 SDRAM SODIMM based on 8Mx16,4Banks,4K Refresh,3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung M464S1724DTS is a 16M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M464S1724DTS consists of eight CMOS 8M x 16 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy
substrate. Three 0.1uF decoupling capacitors are mounted on
the printed circuit board in parallel for each SDRAM. The
M464S1724DTS is a Small Outline Dual In-line Memory Module
and is intended for mounting into 144-pin edge connector sock-
ets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
FEATURE
• Performance range
Part No.
M464S1724DTS-L7C/C7C
M464S1724DTS-L7A/C7A
M464S1724DTS-L1H/C1H
M464S1724DTS-L1L/C1L
Max Freq. (Speed)
133MHz (7.5ns @ CL=2)
133MHz (7.5ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,250mil) , double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1 VSS 2
3 DQ0 4
5 DQ1 6
7 DQ2 8
9 DQ3 10
11 VDD 12
13 DQ4 14
15 DQ5 16
17 DQ6 18
19 DQ7 20
21 VSS 22
23 DQM0 24
25 DQM1 26
27 VDD 28
29 A0 30
31 A1 32
33 A2 34
35 VSS 36
37 DQ8 38
39 DQ9 40
41 DQ10 42
43 DQ11 44
45 VDD 46
47 DQ12 48
49 DQ13 50
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VDD
A3
A4
A5
VSS
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ45
51 DQ14 52 DQ46
53 DQ15 54 DQ47
55 VSS 56 VSS
57 NC 58 NC
59 NC 60 NC
Voltage Key
61 CLK0 62 CKE0
63 VDD 64 VDD
65 RAS 66 CAS
67 W E 68 CKE1
69 CS0 70 *A12
71 CS1 72 *A13
73 DU 74 CLK1
75 VSS 76 VSS
77 NC 78 NC
79 NC 80 NC
81 VDD 82 VDD
83 DQ16 84 DQ48
85 DQ17 86 DQ49
87 DQ18 88 DQ50
89 DQ19 90 DQ51
91 VSS 92 VSS
93 DQ20 94 DQ52
95 DQ21 96
97 DQ22 98
99 DQ23 100
101 VDD 102
103 A6 104
105 A8 106
107 VSS 108
109 A9 110
111 A10/AP 112
113 VDD 114
115 DQM2 116
117 DQM3 118
119 VSS 120
121 DQ24 122
123 DQ25 124
125 DQ26 126
127 DQ27 128
129 VDD 130
131 DQ28 132
133 DQ29 134
135 DQ30 136
137 DQ31 138
139 VSS 140
141 **SDA 142
143 VDD 144
DQ53
DQ54
DQ55
VDD
A7
BA0
V SS
BA1
A11
VDD
DQM6
DQM7
V SS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
V SS
**SCL
VDD
PIN NAMES
Pin Name
Function
A0 ~ A11
Address input (Multiplexed)
BA0 ~ BA1
Select bank
DQ0 ~ DQ63 Data input/output
CLK0 ~ CLK1 Clock input
CKE0 ~ CKE1 Clock enable input
CS0 ~ CS1
Chip select input
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQM0 ~ 7
DQM
VDD
Power supply (3.3V)
VSS
Ground
SDA
Serial data I/O
SCL
Serial clock
DU
Don′t use
NC
No connection
* These pins are not used in this module.
** These pins should be NC in the system
which does not support SPD.
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Sept. 2001