KM62V256C Datasheet, PDF (1/12 Pages) Samsung semiconductor – 32Kx8 bit Low Power AND Low Vcc CMOS Static RAM

KM62V256C, KM62U256C Family
CMOS SRAM
32Kx8 bit Low Power & Low Vcc CMOS Static RAM
FEATURE SUMMARY
GENERAL DESCRIPTION
• Process Technology : 0.7µm CMOS
• Organization : 32K x 8
• Power Supply Voltage
KM62V256C family : 3.3V ± 0.3V
KM62U256C family : 3.0V ± 0.3V
• Low Data Retention Voltage : 2V(Min)
• Three state output and TTL Compatible
• Package Type : JEDEC Standard
28-SOP, 28-TSOP(I)-Forward/Reverse
The KM62V256C and KM62U256C family are fabricated
by SAMSUNG's advanced CMOS process technology. The
family can support various operating temperature ranges
and has various package types for user flexibility of system
design. The family also support low data retention voltage
for battery back-up operation with low data retention
current.
PRODUCT FAMILY
Product
List
Operating _{Vcc Range}
Temp.
Speed
(ns)
KM62V256CL-L Commercial
KM62U256CL-L (0~70 °C)
KM62V256CLE-L Extended
KM62U256CLE-L (-25~85 °C)
KM62V256CLI-L Industrial
KM62U256CLI-L (-40~85 °C)
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
3.0~3.6V
2.7~3.3V
70*/100
85*/100
70*/100
85*/100
70*/100
85*/100
* measured with 30pF test load
** the device with 100ns SOP package in 3.0~3.6V Vcc range is not produced.
PKG Type
28-SOP**
28-TSOP(I) R/F
28-SOP**
28-TSOP(I) R/F
28-SOP**
28-TSOP(I) R/F
Power Dissipation
Standby
(Isb1, Max)
10 µA
Operating
(Icc2)
10 µA
20 µA
15 µA
35mA
20 µA
15 µA
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A14
1
28
Vcc /OE 1
28 A10
A12
2
A11 2
27
/WE _{A9 3}
27 /CS
26 IO8
A7
3
26
A13 A8 4
25 IO7
A13 5
24 IO6
A6
4
25
A8 _{/WE 6}
28-Pin TSOP ^{23 IO5}
A5
5
24
A9 Vcc 7
22 IO4
A4
6
Type I - Forward ^{A14 8}
23
A11 _{A12 9}
21 Vss
20 IO3
A3 7 _{28-Pin SOP} 22 /OE A7 10
19 IO2
A6 11
18 IO1
A2
8
21
A10 _{A5 12}
17 A0
A1
9
20
/CS A4 13
16 A1
A0
10
A3 14
19
I/O8
15 A2
I/O1
11
18
I/O7
I/O2
12
I/O3
13
Vss
14
17
I/O6
A3
14
28 A2
16
I/O5 A4 13
27 A1
15
I/O4 ^A5
A6
12
11
26 A0
25 IO1
A7 10
A12 9
28-Pin TSOP
24 IO2
23 IO3
A14 8
Vcc 7
Type I - Reverse
22
21
Vss
IO4
/WE 6
20 IO5
A13 5
19 IO6
A8 4
18 IO7
A9 3
17 IO8
A11 2
16 /CS
/OE 1
15 A10
A0~2, A9~11
A3~A8
A12~14
Y-Decoder
Cell Array
I/O1~8
I/O Buffer
/CS, /WE
/OE
Pin Name
A0~A14
/WE
/CS
/OE
I/O1~I/O8
Vcc
Vss
Function
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Input/Output
Power
Ground
-1-
ELECTRONICS
Revision 04
April 1996