KM6264B Datasheet, PDF (1/10 Pages) Samsung semiconductor – 8Kx8 bit Low Power CMOS Static RAM

KM6264B Family
8Kx8 bit Low Power CMOS Static RAM
CMOS SRAM
FEATURE SUMMARY
• Process Technology : CMOS
• Organization : 8K x 8
• Power Supply Voltage : Single 5V ± 10%
• Low Data Retention Voltage : 2V(Min)
• Three state output and TTL Compatible
• Package Type : JEDEC Standard
28-DIP, 28-SOP
GENERAL DESCRIPTION
The KM6264B family is fabricated by SAMSUNG's
advanced CMOS process technology. The family
can support various operating temperature ranges
and has various package types for user flexibility of
system design. The family also support low data
retention voltage for battery back-up operations with
low data retention current.
PRODUCT FAMILY
Product
Family
KM6264BL
KM6264BL-L
KM6264BLE
KM6264BLE-L
KM6264BLI
KM6264BLI-L
Operating
Temperature
Speed
PKG Type
Power Dissipation
Standby(Isb1, Max) Operating(Icc2)
Commercial
(0~70 °C) ^{70/100/120ns 28-DIP, 28-SOP}
Extended
(-25~-85 °C)
100*ns
28-SOP
Industrial
(-40~85 °C)
100*ns
28-SOP
100uA
10uA
100uA
50uA
100uA
50uA
55mA
* measured with 30pF test load
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
N.C
1
28
Vcc
A12
2
27
/WE
A7
3
26
CS2
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3 7 _{28-Pin DIP} 22 /OE
A2 8 _{28-Pin SOP} 21 A10
A1
9
20
/CS1
A0
10
19
I/O8
I/O1
11
18
I/O7
I/O2
12
17
I/O6
I/O3
13
16
I/O5
Vss
14
15
I/O4
Y-Decoder
A0~A12
Cell Array
I/O1~8
I/O Buffer
/CS1, CS2
/WE, /OE
Pin Name
A0~A12
/WE
/CS1, CS2
/OE
I/O1~I/O8
Vcc
Vss
N.C
Function
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Input/Output
Power(5V)
Ground
No Connection
1
ELECTRONICS
Revision. 0.0
Auust. 1996