KM611001 Datasheet, PDF (1/8 Pages) Samsung semiconductor – 1M x 1Bit High-Speed CMOS SRAM

KM611001/L
CMOS SRAM
1M x 1Bit High-Speed CMOS SRAM
FEATURES
• Fast Access Time 20, 25, 35ns(Max.)
• Low Power Dissipation
Standby (TTL) : 40 mA(Max.)
(CMOS): 2 mA(Max.)
0.5 mA(Max.) - L-ver.
Operating KM611001/L -20 : 130 mA(Max.)
KM611001/L -25 : 110 mA(Max.)
KM611001/L -35 : 100 mA(Max.)
• Single 5.0V ± 10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Low Data Retention Voltage : 2V(Min.)- L-Ver Only
• Standard Pin Configuration
KM611001P/LP : 28-DIP-400
KM611001J/LJ : 28-SOJ-400A
GENERAL DESCRIPTION
The KM611001/L is a 1,048,576-bit high-speed Static
Random Access Memory organized as 1,048,576
words by 1 bit. The KM611001/L has separate input
and output lines for fast read and write access. The
device is fabricated using Samsung`s advanced
CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-
density high-speed system applications. The
KM611001/L is packaged in a 400 mil 28-pin plastic DIP
or SOJ.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
A0
A1
A2
A3
A5
A6
A7
A8
A9
DIN
DOUT
MEMORY ARRAY
512 Rows
2048x1 Columns
Data
Cont.
Clk
Gen.
I/O Circuit
Column Select
A4 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
/CS
/WE
PIN CONFIGURATION(TOP VIEW)
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
N.C 7
A6 8
A7 9
A8 10
A9 11
DOUT 12
/WE 13
Vss 14
SOJ/DIP
28 Vcc
27 A19
26 A18
25 A17
24 A16
23 A15
22 A14
21 N.C
20 A13
19 A12
18 A11
17 A10
16 DIN
15 /CS
PIN DESCRIPTION
Pin Name
Pin Function
A0-A19
/WE
/CS
DIN
DOUT
Vcc
Vss
N.C
Address Inputs
Write Enable
Chip Select
Data Input
Data Output
Power (+5V)
Ground
No Connection
1
Rev 2.0
July-1996