KM48S16030 Datasheet, PDF (1/10 Pages) Samsung semiconductor – 4M x 8Bit x 4 Banks Synchronous DRAM

KM48S16030
4M x 8Bit x 4 Banks Synchronous DRAM
Preliminary
CMOS SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS Latency (2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The KM48S16030 is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clcok
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Part NO.
KM48S16030T-G/F8
KM48S16030T-G/FH
KM48S16030T-G/FL
KM48S16030T-G/F10
MAX Freq.
125MHz
100MHz
100MHz
100MHz
Interface Package
LVTTL
54pin
TSOP(II)
Data Input Register
Bank Select
CLK
ADD
4M x 8
4M x 8
4M x 8
4M x 8
Column Decoder
LCKE
LRAS
LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
REV. 2 Mar. '98