KM48C8004B Datasheet, PDF (1/21 Pages) Samsung semiconductor – 8M x 8bit CMOS Dynamic RAM with Extended Data Out

KM48C8004B, KM48C8104B
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5 or -6), package type (SOJ or TSOP-
II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
This 8Mx8 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power con-
sumption and high reliability.
FEATURES
• Part Identification
- KM48C8004B(5.0V, 8K Ref.)
- KM48C8104B(5.0V, 4K Ref.)
• Active Power Dissipation
Speed
8K
-45
550
-5
495
-6
440
• Refresh Cycles
Unit : mW
4K
715
660
605
Part
NO.
KM48C8004B*
KM48C8104B
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
• Performance Range
Speed tRAC
tCAC
-45
45ns 12ns
-5
50ns 13ns
-6
60ns 15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +5.0V±10% power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
Vcc
Vss
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A9
(A0~A10)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
8,388,608 x 8
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
DQ0
to
DQ7
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.