KM48C2000B Datasheet, PDF (1/8 Pages) Samsung semiconductor – 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode

KM48C2000B, KM48C2100B
KM48V2000B, KM48V2100B
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode
CMOS DRAM
DESCRIPTION
This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5,-6 or -7), power con-
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power
consumption and high reliability.
It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
¡Ü Part Identification
- KM48C2000B/B-L (5V, 4K Ref.)
- KM48C2100B/B-L (5V, 2K Ref.)
- KM48V2000B/B-L (3.3V, 4K Ref.)
- KM48V2100B/B-L (3.3V, 2K Ref.)
¡Ü Active Power Dissipation
Speed
-5
-6
-7
3.3V
4K
2K
324
396
288
360
252
324
Unit : mW
5V
4K
2K
495
605
440
550
385
495
¡Ü Refresh Cycles
Part
NO.
C2000B
V2000B
C2100B
V2100B
VCC
5V
3.3V
5V
3.3V
Refresh
cycle
4K
2K
Refresh period
Normal L-ver
64ms
32ms
128ms
¡Ü Performance Range
Speed
-5
-6
tRAC
50ns
60ns
tCAC
13ns
15ns
-7 70ns 20ns
tRC
90ns
110ns
130ns
tPC
35ns
40ns
45ns
Remark
5V/3.3V
5V/3.3V
5V/3.3V
¡Ü Fast Page Mode operation
¡Ü Byte/Word Read/Write operation
¡Ü CAS-before-RAS refresh capability
¡Ü RAS-only and Hidden refresh capability
¡Ü Self-refresh capability (L-ver only)
¡Ü Fast parallel test mode capability
¡Ü TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
¡Ü Early Write or output enable controlled write
¡Ü JEDEC Standard pinout
¡Ü Available in Plastic SOJ and TSOP(II) packages
¡Ü Single +5V¡¾10% power supply (5V product)
¡Ü Single +3.3V¡¾0.3V power supply (3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
A0-A11
(A0 - A10)*1
A0 - A8
(A0 - A9)*1
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
2,097,152 x 8
Cells
Column Decoder
Vcc
Vss
Data in
Buffer
DQ0
to
DQ7
Data out
Buffer
OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.