KM44C4005C Datasheet, PDF (1/20 Pages) Samsung semiconductor – 4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out

KM44C4005C, KM44C4105C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high
speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access
time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of
this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is avail-
able in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-
width, low power consumption and high reliability.
FEATURES
• Part Identification
- KM44C4005C/C-L (5V, 4K Ref.)
- KM44C4105C/C-L (5V, 2K Ref.)
• Active Power Dissipation
Unit : mW
Speed
Refresh Cycle
4K
2K
-5
495
605
-6
440
550
• Extended Data Out mode operation
(Fast Page Mode with Extended Data Out)
• Four separate CAS pins provide for separate I/O operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply
• Refresh Cycles
Part
Refresh
NO.
cycle
C4005C
4K
C4105C
2K
Refresh period
Normal
L-ver
64ms
32ms
128ms
• Performance Range
Speed tRAC
tCAC
-5
50ns
13ns
-6
60ns
15ns
tRC
84ns
104ns
tHPC
20ns
25ns
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS0 - 3
W
A0-A11
(A0 - A10) *1
A0 - A9
(A0 - A10) *1
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
4,194,304 x 4
Cells
Column Decoder
Vcc
Vss
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.