KM44C1000D Datasheet, PDF (1/21 Pages) Samsung semiconductor – 1M x 4Bit CMOS Dynamic RAM with Fast Page Mode

KM44C1000D, KM44V1000D
CMOS DRAM
1M x 4Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 4bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power), and
package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, self-refresh operation is available in 3.3V Low power version.
This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and high per-
formance microprocessor systems.
FEATURES
• Part Identification
- KM44C1000D/D-L(5V, 1K Ref.)
- KM44V1000D/D-L(3.3V, 1K Ref.)
• Active Power Dissipation
Speed
-5
-6
-7
3.3V
-
220
200
Unit : mW
5V
470
415
360
• Refresh Cycles
Part
Refresh
NO.
cycle
KM44C1000D
1K
KM44V1000D
Refresh Period
Normal L-ver
16ms 128ms
• Performance Range
Speed tRAC tCAC tRC
-5 50ns 15ns 90ns
-6 60ns 15ns 110n
-7 70ns 20ns 130n
tPC
35ns
40ns
45ns
Remark
5V only
5V/3.3V
5V/3.3V
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (3.3V, L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early write or output enable controlled write
• JEDEC Standard pinout
• Available in 26(20)-pin SOJ 300mil and TSOP(II)
300mil packages
• Single +5V±10% power supply(5V product)
• Single +3.3V±0.3V power supply(3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
Vcc
Vss
VBB Generator
A0~A9
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
1,048,576 x4
Cells
Column Decoder
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.