KM416C256D Datasheet, PDF (1/8 Pages) Samsung semiconductor – 256K x 16Bit CMOS Dynamic RAM with Fast Page Mode

KM416C256D, KM416V256D
CMOS DRAM
256K x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 262,144 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5,-6,-7), power consumption(Normal or Low power) and
package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and
Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 fast page mode DRAM family is
fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability.
It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
¡Ü Part Identification
- KM416C256D/DL (5V, 512K Ref.)
- KM416V256D/DL (3.3V, 512K Ref.)
¡Ü Active Power Dissipation
Speed
-5
-6
-7
3.3V(512 Ref.)
-
325
290
Unit : mW
5V(512 Ref.)
605
495
440
¡Ü Refresh Cycles
Part
NO.
C256D
V256D
VCC
5V
3.3V
Refresh
cycle
512K
Refresh period
Normal L-ver
8ms
128ms
¡Ü Performance Range:
Speed
-5
-6
-7
tRAC
50ns
60ns
70ns
tCAC
15ns
15ns
20ns
tRC
90ns
10ns
130ns
tPC
35ns
40ns
45ns
Remark
5V only
5V/3.3V
5V/3.3V
¡Ü Fast Page Mode operation
¡Ü 2 CAS Byte/Wrod Read/Write operation
¡Ü CAS-before-RAS refresh capability
¡Ü RAS-only and Hidden refresh capability
¡Ü Self-refresh capability (L-ver only)
¡Ü TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
¡Ü Early Write or output enable controlled write
¡Ü JEDEC Standard pinout
¡Ü Available in 40-pin SOJ 400mil and44(40)-pin
TSOP(II) 400mil packages
¡Ü Triple +5V¡¾10% power supply(5V product)
¡Ü Triple +3.3V¡¾0.3V power supply(3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
UCAS
LCAS
W
A0
.
.
A8
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
262,144 x16
Cells
Column Decoder
Vcc
Vss
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
DQ8
to
DQ15
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.