K4X1G323PC-L Datasheet, PDF (1/20 Pages) Samsung semiconductor – 32Mx32 Mobile DDR SDRAM

K4X1G323PC - L(F)E/G
Mobile DDR SDRAM
32Mx32 Mobile DDR SDRAM
1. FEATURES
• VDD/VDDQ = 1.8V/1.8V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• MRS cycle with address key programs
- CAS Latency ( 3 )
- Burst Length ( 2, 4, 8, 16 )
- Burst Type (Sequential & Interleave)
• EMRS cycle with address key programs
- Partial Array Self Refresh ( Full, 1/2, 1/4 Array )
- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )
• Internal Temperature Compensated Self Refresh
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).
• Data I/O transactions on both edges of data strobe, DM for masking.
• Edge aligned data output, center aligned data input.
• No DLL; CK to DQS is not synchronized.
• DM0 - DM3 for write masking only.
• Auto refresh duty cycle
- 7.8us for -25 to 85 °C
2. Operating Frequency
Speed @CL2¹⁾
Speed @CL3¹⁾
NOTE :
1) CAS Latency
3. Address configuration
Organization
32Mx32
- DM is internally loaded to match DQ and DQS identically.
DDR333
83Mhz
166Mhz
Bank Address
BA0,BA1
DDR266
83Mhz
133Mhz
Row Address
A0 - A12
Column Address
A0 - A9
4. Ordering Information
Part No.
K4X1G323PC-7(8)E/GC6
K4X1G323PC-7(8)E/GC3
Max Freq.
166MHz(CL=3),83MHz(CL=2)
133MHz(CL=3),83MHz(CL=2)
- 7(8)E : 90FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C)
- 7(8)G : 90FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C)
- C6/C3 : 166MHz(CL=3) / 133MHz(CL=3)
Interface
LVCMOS
Package
90FBGA
Pb (Pb Free)
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Sept 2007