K4S281632B-N Datasheet, PDF (1/8 Pages) Samsung semiconductor – 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP

K4S281632B-N
shrink-TSOP
2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP
CMOS SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page)
- Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The K4S281632B-N is 134,217,728 bits synchronous high
data rate Dynamic RAM organized as 4 x 2,097,152 words by
16 bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part No.
K4S281632B-NC/L1H
K4S281632B-NC/L1L
Max Freq. Interface Package
100MHz(CL=2)
100MHz(CL=3)
LVTTL
54pin
sTSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Data Input Register
CLK
ADD
Bank Select
2M x 16
2M x 16
2M x 16
2M x 16
Column Decoder
LCKE
LRAS LCBR
LWE
LCAS
Latency & Burst Length
Programming Register
LWCBR
Timing Register
LWE
LDQM
DQi
LDQM
CLK
CKE
CS
RAS
CAS
WE
LDQM UDQM
* Samsung Electronics reserves the right to change products or specification without notice.