K4F660812D Datasheet, PDF (1/20 Pages) Samsung semiconductor – 8M x 8bit CMOS Dynamic RAM with Fast Page Mode

K4F660812D,K4F640812D
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are
optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Fur-
thermore, Self-refresh operation is available in L-version. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsung′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4F660812D-JC/L(3.3V, 8K Ref., SOJ)
- K4F640812D-JC/L(3.3V, 4K Ref., SOJ)
- K4F660812D-TC/L(3.3V, 8K Ref., TSOP)
- K4F640812D-TC/L(3.3V, 4K Ref., TSOP)
• Active Power Dissipation
Speed
8K
-45
324
-50
288
-60
252
Unit : mW
4K
432
396
360
• Refresh Cycles
Part
NO.
K4F660812D*
K4F640812D
Refresh
cycle
8K
4K
Refresh time
Normal L-ver
64ms 128ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
• Performance Range
Speed tRAC
tCAC
-45
45ns 12ns
-50
50ns 13ns
-60
60ns 15ns
tRC
80ns
90ns
110ns
tPC
31ns
35ns
40ns
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
Vcc
Vss
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A9
(A0~A10)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
8,388,608 x 8
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
DQ0
to
DQ7
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.