K4F170811D Datasheet, PDF (1/20 Pages) Samsung semiconductor – 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode

K4F170811D, K4F160811D
K4F170812D, K4F160812D
CMOS DRAM
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power con-
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
• Part Identification
- K4F170811D-B(F) (5V, 4K Ref.)
- K4F160811D-B(F) (5V, 2K Ref.)
- K4F170812D-B(F) (3.3V, 4K Ref.)
- K4F160812D-B(F) (3.3V, 2K Ref.)
• Active Power Dissipation
Speed
-50
-60
3.3V
4K
2K
324
396
288
360
Unit : mW
5V
4K
2K
495
605
440
550
• Refresh Cycles
Part
VCC ^{Refresh Refresh period}
NO.
cycle _{Normal L-ver}
K4F170811D 5V
4K
K4F170812D 3.3V
K4F160811D 5V
2K
K4F160812D 3.3V
64ms
32ms
128ms
• Performance Range
Speed tRAC
-50 50ns
tCAC
13ns
-60 60ns 15ns
tRC
90ns
110ns
tPC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
A0-A11
(A0 - A10)*1
A0 - A8
(A0 - A9)*1
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
2,097,152 x 8
Cells
Column Decoder
Vcc
Vss
Data in
Buffer
DQ0
to
DQ7
Data out
Buffer
OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.