K4E661612D Datasheet, PDF (1/36 Pages) Samsung semiconductor – CMOS DRAM

Industrial Temperature
K4E661612D,K4E641612D
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Nor-
mal or Low power) are optional features of this family. All of this family have C A S -before-R A S refresh, R A S -only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated
u s i n g S a m s u n g ′s a d v a n c e d C M O S p r o c e s s t o r e a l i z e h i g h b a n d - w i d t h , l o w p o w e r c o n s u m p t i o n a n d h i g h r e l i a b i l i t y .
FEATURES
• Part Identification
- K4E661612D-TI/P(3.3V, 8K Ref.)
- K4E641612D-TI/P(3.3V, 4K Ref.)
• Active Power Dissipation
Speed
-45
-50
-60
8K
324
288
252
Unit : m W
4K
468
432
396
• Refresh Cycles
Part
NO.
Refresh
cycle
Refresh time
Normal
L-ver
K4E661612D*
8K
64ms
128ms
K4E641612D
4K
* Access mode & R A S only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
C A S - b e f o r e -R A S & H i d d e n r e f r e s h m o d e
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
• Performance Range
Speed
-45
tR A C
45ns
tC A C
12ns
-50
50ns
13ns
-60
60ns
15ns
tRC
74ns
84ns
104ns
tH P C
17ns
20ns
25ns
• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• C A S-before-R A S refresh capability
• R A S-only and Hidden refresh capability
• Fast parallel test mode capability
• Self-refresh capability (L-ver only)
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) packages
• +3.3V ±0.3V power supply
• Industrial Temperature operating ( - 4 0 ~ 8 5°C )
FUNCTIONAL BLOCK DIAGRAM
RAS
UCAS
LCAS
W
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
4,194,304 x 16
Cells
Column Decoder
Vcc
Vss
Lower
Data in
Buffer
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
DQ0
to
DQ7
OE
D Q8
to
DQ15
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change products and specifications without notice.