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K4E660412D Datasheet, PDF (1/21 Pages) Samsung semiconductor – 16M x 4bit CMOS Dynamic RAM with Extended Data Out
K4E660412D,K4E640412D
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 EDO Mode DRAM family is fabricated
using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4E660412D-JC/L(3.3V, 8K Ref., SOJ)
- K4E640412D-JC/L(3.3V, 4K Ref., SOJ)
- K4E660412D-TC/L(3.3V, 8K Ref., TSOP)
- K4E640412D-TC/L(3.3V, 4K Ref., TSOP)
• Active Power Dissipation
Speed
8K
-45
324
-50
288
-60
252
Unit : mW
4K
432
396
360
• Refresh Cycles
Part
NO.
K4E660412D*
K4E640412D
Refresh
cycle
8K
4K
Refresh time
Normal L-ver
64ms 128ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
• Performance Range
Speed
-45
tRAC
45ns
tCAC
12ns
-50
50ns 13ns
-60
60ns 15ns
tRC
74ns
84ns
104ns
tHPC
17ns
20ns
25ns
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
Vcc
Vss
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
16,777,216 x 4
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
DQ0
to
DQ3
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.