K4E170411D Datasheet, PDF (1/21 Pages) Samsung semiconductor – 4M x 4Bit CMOS Dynamic RAM with Extended Data Out

K4E170411D, K4E160411D
K4E170412D, K4E160412D
CMOS DRAM
4M x 4Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4.194,304 x 4 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K
Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of
this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh
operation is available in L-version. This 4Mx4 EDO DRAM family is fabricated using Samsung′s advanced CMOS process to realize high
band-width, low power consumption and high reliability. It may be used as main memory unit for high level computer, microcomputer and
personal computer.
FEATURES
• Part Identification
- K4E170411D-B(F) (5V, 4K Ref.)
- K4E160411D-B(F) (5V, 2K Ref.)
- K4E170412D-B(F) (3.3V, 4K Ref.)
- K4E160412D-B(F) (3.3V, 2K Ref.)
• Active Power Dissipation
Speed
-50
-60
3.3V
4K
2K
324
396
288
360
Unit : mW
5V
4K
2K
495
605
440
550
• Refresh Cycles
Part
VCC ^{Refresh Refresh period}
NO.
cycle _{Normal L-ver}
K4E170411D 5V
4K
K4E170412D 3.3V
K4E160411D 5V
2K
K4E160412D 3.3V
64ms
32ms
128ms
• Performance Range
Speed tRAC
-50 50ns
tCAC
15ns
-60 60ns 17ns
tRC
84ns
104ns
tHPC
20ns
25ns
Remark
5V/3.3V
5V/3.3V
• Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
A0-A11
(A0 - A10)*1
A0 - A9
(A0 - A10)*1
Control
Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Memory Array
4,194,304 x4
Cells
Column Decoder
Vcc
Vss
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.