STUD420S Datasheet, PDF (1/8 Pages) SamHop Microelectronics Corp. – S uper high dense cell design for low R DS (ON).

S T U/D420S
S amHop Microelectronics C orp.
J uly 05,2006
N-C hannel Logic Level E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
VDS S
40V
ID
R DS (ON) ( m Ω ) Max
24 @ VGS = 10V
24A
30 @ VGS = 4.5V
F E AT UR E S
S uper high dense cell design for low R DS(ON).
R ugged and reliable.
TO-252 and TO-251 P ackage.
D
G
S
S TU S E R IE S
T O -252AA(D-P AK )
G
DS
S TD S E R IE S
TO-251(l-P AK)
D
G
S
ABS OLUTE MAXIMUM R ATINGS (TA=25 C unless otherwise noted)
P arameter
Drain-S ource Voltage
S ymbol
Limit
Unit
VDS
40
V
Gate-S ource Voltage
VGS
20
V
Drain C urrent-C ontinuous ^a @ TC=25 C
ID
24
A
-P ulsed ^b
IDM
75
A
Drain-S ource Diode Forward C urrent
IS
8
A
Maximum P ower Dissipation @ Tc=25 C
PD
50
W
Operating and S torage Temperature R ange _{TJ, TS TG}
-55 to 175
C
THE R MAL CHAR ACTE R IS TICS
Thermal R esistance, Junction-to-C ase
R JC
3
C /W
Thermal R esistance, Junction-to-Ambient
R JA
50
C /W
1