STU419S Datasheet, PDF (1/8 Pages) SamHop Microelectronics Corp. – P-Channel Logic Level EnhancementMode Field E ffect Transistor

S amHop Microelectronics C orp.
S T U/D419S
Mar,29, 2007
P -C hannel Logic Level E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
VDS S
ID
R DS (ON) ( m W ) Max
-40V -40A
9 @ VGS = -10V
12 @ VGS = -4.5V
F E AT UR E S
S uper high dense cell design for low R DS(ON).
R ugged and reliable.
S urface Mount P ackage.
E S D P rocteced
D
D
G
S
S TU S E R IE S
T O -252AA(D-P AK )
G
DS
S TD S E R IE S
TO-251(l-P AK)
G
S
AB S OL UTE MAXIMUM R ATINGS (TA=25 C unles s otherwis e noted)
P arameter
S ymbol
Limit
Unit
Drain-S ource Voltage
VDS
-40
V
Gate-S ource Voltage
VGS
20
V
a
25 C
-40
A
Drain C urrent-C ontinuous @ Ta
ID
70 C
-32
A
-P ulsed ^b
IDM
-100
A
Drain-S ource Diode Forward C urrent ^a
IS
-10
A
Ta= 25 C
50
Maximum P ower Dissipation ^a
PD
W
Ta=70 C
35
Operating Junction and S torage
Temperature R ange
TJ, TSTG
-55 to 175
C
THE R MAL CHAR ACTE R IS TICS
Thermal R esistance, Junction-to-C ase
R JC
3
C /W
Thermal R esistance, Junction-to-Ambient
R JA
50
C /W
1