BU9729K Datasheet, PDF (9/12 Pages) Rohm – Segment-type LCD driver

Standard ICs
BU9729K
DDRAM addresses set for the address counter are in hexadecimal format, and are displayed as shown below.
MSB
LSB
AC4
AC3
AC2
AC1
AC0
(Example) When the DDRAM address is "11" (display position: SEG18)
MSB
LSB
1
0
0
0
1
1
1
Display data input to the command / data register (C / D = LOW) is divided into the first four bits and the last four
bits, with the specified DDRAM address being written to the first four, and the specified address + 1 being written to
the last four. The four bits of display data are written sequentially to the bits of the DDRAM, starting from the MSB on
both sides.
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
Specified address
(bit3
bit0)
Specified address + 1
(bit3
bit0)
When a DDRAM Write command is input (C / D = HIGH), the four bits of display data in the DDRAM Write command
are written to the specified DDRAM address. The four bits are written sequentially, starting from the MSB, to the bits
of the DDRAM, starting with the MSB of the DDRAM.
MSB
LSB
1
0
0
∗
D3
D2
D1
D0
DDRAM Write command
Display data
(bit3
bit0)
(4) Timing generator
Connecting Rf between OSC1 and OSC2 causes oscillation of the internal oscillator circuit and generates a display
timing signal. Operation can also be initiated by inputting an external clock.
OSC1
OSC2
Rf
(Rf can be used
to change the
oscillation
frequency.)
OSC1
EXIT CLOCK INPUT
OSC2
OPEN
Fig. 4 Rf oscillator circuit
Fig. 5 External clock input
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