BU2050F_1 Datasheet, PDF (9/25 Pages) Rohm – Serial / Parallel 4-input Drivers

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
【BU2092F/BU2092FV】
●Pin descriptions
Pin No. Pin Name
1
V_SS
2
DATA
3
CLOCK
4
LCK
5～11,
14～18
Q0～Q11
12, 13
17
18
●Timing chart
N.C.
OE
V_DD
CLOCK
I/O
Function
-
GND
I
Serial Data Input
I
Shift clock of DATA (Rising Edge Trigger)
I
Latch clock of DATA (Rising Edge Trigger)
Parallel Data Output (Nch Open Drain FET)
O
Latch Data
L
H
Output FET
ON
OFF
-
Non connected
I
Output Enable (“H” level : output FET is OFF)
-
Power Supply
DATA
DATA11 DATA10 DATA9
DATA1
DATA0
Technical Note
LCK
OE
Qx
“H”
Previous DATA
DATA11～0
Note) Diagram shows a status where a pull-up resistor is connected to output.
Fig. 4
1. After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits into
the DATA terminal.
2. Qx parallel output data of the shift register is set after the 12^th clock by the LCK.
3. Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
4. Data retained in the internal latch circuit is output when the OE is in the “L” section.
ï¼»Truth Tableï¼½
CLOCK
×
×
Input
DATA
LCK
×
×
×
×
L
×
H
×
×
×
×
×
×
×
OE
Function
H
Output (Q0～Q11) Disable
L
Output (Q0～Q11) Enable
×
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
×
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
×
The data of shift register has no change.
×
The data of shift register is transferred to the storage register.
×
The data of storage register has no change.
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2009.06 - Rev.A