BD9560MUV_10 Datasheet, PDF (9/22 Pages) Rohm – Switching Regulator Controller for Graphic Chip Cores

BD9560MUV
● Timing Chart
・Soft Start Function
VRON
TSS
SS
VOUT
IIN
・Timer Latch Type Short Circuit Protection
VDAC×0.7
VOUT
TSCP
SCP
VRON/UVLO
・Output Over Voltage Circuit Protection
VOUT
1.5V
HG
LG
Switching
・Power good function
VOUT
VOUT-300mV
TPWRGD
PWRGD_C
PWRGD
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Technical Note
Soft start is exercised with the VRON pin set high.
Current control takes effect at startup, enabling a
moderate output voltage “ramping start.” Soft start
timing and incoming current are calculated with
formulas (1) and (2) below.
Soft start time
Tss= ^VDAC×Css [sec] ・・・(1)
2μA(typ)
Incoming current
IIN= ^Co×VOUT [A] ・・・(2)
Tss
(Css: Soft start capacitor; Co: Output capacitor)
Short protection kicks in when output falls to or below
(VDAC X0.7).
When the programmed time period elapses, output is
latched OFF to prevent destruction of the IC. Output
voltage can be restored either by reconnecting the
VRON pin or disabling UVLO. Short Circuit Protection
timing is calculated with formulas (3) below.
Short Circuit Protection time
Tscp= ^{1.2(V)×CSCP} [sec] ・・・(3)
2μA(typ)
Over voltage protection kicks and low side FET is the
status of full ON in when output is up to 1.5V or more
（LG=High、HG=Low）. It is operated ordinary with
falling of output.
Power good function kicks in when output is from
(VOUT-300mV) to (VOUT+200mV). After setting, power
good pin is the status of high. (Pull up the resistance
outside) Delay timing of power good is calculated with
formulas (4) below.
Power good delay time
TPWRGD = ^{1.2(V)×CPWRGD_C} [sec] ・・・(4)
2μA(typ)
(CPWRGD : PWRGD_C pin capacitor)
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2010.04 - Rev.C