BU91797MUF-M Datasheet, PDF (8/27 Pages) Rohm – Low Duty LCD Segment Driver for Automotive application

BU91797MUF-M MAX 144 segments (SEG36×COM4)
Command Transfer Method
Issue Slave Address (“01111100”) after generating “START condition”.
The 1^st byte after Slave Address always becomes command input.
MSB (“command or data judge bit”) of command decide to next data is command or display data.
When set “command or data judge bit”=‘1’, next byte will be command.
When set “command or data judge bit”=‘0’, next byte data is display data.
Datasheet
S Slave address A 1 Command A 1 Command A 1 Command A 0 Command A Display Data … P
It cannot accept input command once it enters into display data transfer state.
In order to input command again it is necessary to generate “START condition”.
If “START condition” or “STOP condition” is sent in the middle of command transmission, command will be cancelled.
If Slave address is continuously sent following “START condition”, it remains in command input state.
“Slave address” must be sent right after the “START condition”.
When Slave Address cannot be recognized in the first data transmission, no Acknowledge bit is generated and next
transmission will be invalid. When data is invalid status, if “START condition” is transmitted again, it will return to valid
status.
Consider the MPU interface characteristic such as Input rise time and Setup/Hold time when transferring command and
data (Refer to MPU Interface).
Write Display and Transfer Method
BU91797MUF-M has Display Data RAM (DDRAM) of 36×4=144bit.
The relationship between data input and display data, DDRAM data and address are as follows;
Slave address
Command
S 01111100 A 0 0000000 _{A a b c d e f g h A i j k l m n o p}
A…P
Display Data
8-bit data is stored in DDRAM. ADSET command specifies the address to be written, and address is automatically
incremented in every 4-bit data.
Data can be continuously written in DDRAM by transmitting data continuously.
When RAM data is written successively, after writing RAM data to 23h (SEG35), the address is returned to 00h (SEG0) by
the auto-increment function
DDRAM address
00 01 02 03 04 05 06 07
0a
e
i
m
1b
f
j
n
BIT _{2 c}
g
k
o
3d
h
l
p
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
・・・
21h 22h 23h
COM0
COM1
COM2
COM3
SEG33 SEG34 SEG35
Display data is written to DDRAM every 4-bit data.
No need to wait for ACK bit to complete data transfer.
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