BHXXPB1WHFV_09 Datasheet, PDF (8/10 Pages) Rohm – CMOS LDO Regulators with Auto Power Saving Function

BH□□PB1WHFV Series
Technical Note
6. Overcurrent protection circuit
The IC incorporates a built-in overcurrent protection circuit that operates according to the output current capacity. This circuit
serves to protect the IC from damage when the load is shorted. The protection circuit is designed to limit current flow by not
latching in the event of a large and instantaneous current flow originating from a large capacitor or other component. These
protection circuits are effective in preventing damage due to sudden and unexpected accidents. However, the IC should not
be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of
thermal designing, keep in mind that the current capability has negative characteristics to temperatures.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction.
8. Back Current
In applications where the IC may be exposed to back current flow, it is recommended to create a path to dissipate this
current by inserting a bypass diode between the VIN and VOUT pins.
Back current
VIN
OUT
STBY GND
Fig. 32 Example Bypass Diode Connection
9. I/O voltage difference
Using the IC in automatic switching mode when the I/O voltage differential becomes saturated (VIN - VOUT < 150 mV)
may result in a large output noise level. If the noise level becomes problematic, use the IC with the SEL pin in the high
state when the voltage differential is saturated.
10.GND Voltage
The potential of GND pin must be minimum potential in all operating conditions.
11. Preventing Rush Current
By attaching the Rss and Css time constants to the STBY pin, sudden rises in the regulator output voltage can be
prevented, dampening the flow of rush current to the output capacitors. The larger the time constant used, the greater the
resulting reduction. However, large time constants also result in longer startup times, so the constant should be selected
after considering the conditions in which the IC is to be used.
100
Rss = 10 k
IO = no load
10
1.0 m
100 
0.01 
0.1 
1.0 
Slow s_Fta_rr_et_qc_ua_ep_na_cc_yita_f[n_Hc_ze_]Css (F)
Fig. 33 VOUT Startup Time vs CSS Capacitance (Reference)
12. Regarding input Pin of the IC (Fig.34)
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
Pin A
Pin B _C B
Pin B
Pin A
E
N
N ^P+
Parasitic element
P
P⁺ _N
P substrate
GND
Parasitic
element
N _P+
Parasitic element
Fig.34
N
P
P⁺ _N
P substrate
GND
GND
B
C
E
Parasitic
element
GND
Other adjacent elements
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2009.04 - Rev.A