BD57011GWL Datasheet, PDF (8/22 Pages) Rohm – Low Impedance FET in rectifier

BD57011GWL
Description of Block
1) Rectifier block
According to electromagnetic induction phenomena, electromotive force occurs in a secondary side coil in inputting AC signal
into the both ends of a primary side (TX) coil. Full-wave rectification by switching operation is realized by detecting output
current from the coil generated from the above-mentioned operation, making on/offf built-in FET connected to AC1 and AC2
terminal based on the detection signal, outputting current to RECT, and charging REC terminal external capacity.
Detecting a coil current to compare AC terminal voltage (FET Ron x Icoil) with GND level, it detects the timing set to 0 mA.
The on/off signal of built-in FET is generated based on this detection signal. The on/off timing of L side FET and H side FET was
generated, and penetration current is prevented.
The bootstrap drive system which sets the H side-L side to Nch FET is adopted for high efficiency. Therefore, the capacitor for
voltage maintenance is needed for BOOT1 (BOOT2) terminal to AC1 (AC2) terminal.
2) Low Drop Out (LDO) block
OUT terminal output voltage can be freely set up by external resistance. It assumes that system load (PMIC) including a
charger is connected to an OUT terminal. In order to suppress heating on the whole set, it recommends carrying out an OUT
setup near the full charge voltage of the Li-ion battery.
An error signal is returned to the TX side so that the input-and-output difference of RECT and OUT may become the minimum.
An input-and-output difference is made small, so that load is large, and heating of IC simple substance is suppressed.
The relation between Iout and desired point (voltage which RECT terminal voltage converges) is as follows.
RECT desired point
OUT
ILIM
Iout
Figure 9. RECT desired point
Output voltage becomes settled uniquely in the resistance (E24 series) connected to an OUTSET terminal.
It can choose from the 16 following steps.
Step
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUT setting[V]
4.30
4.35
4.40
4.45
4.50
4.55
4.60
4.65
4.70
4.75
4.80
4.90
5.00
5.10
5.20
5.30
RSET[kΩ](E24)
180
120
91
75
62
56
47
43
39
36
33
30
27
24
22
20
Reference ^adjust
LDO
Voltage
adjustable
OUT
Iout
ADC
BD57011GWL
I/V
conv.
OUTSET
RSET
Figure 10. OUTSET circuit
An OUTSET terminal cannot be used by OPEN. Please be sure to use it, connecting resistance.
Moreover, you can’t change OUTSET setting during operation.
You need to apply a load after OUT output due to OCP limitation.
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TSZ22111・15・001
8/19
TSZ02201-0F2F0AK00110-1-2
2.Jul.2015 Rev.002