BU9797FUV-M Datasheet, PDF (7/28 Pages) Rohm – Integrated Buffer AMP for LCD Driving

BU9797FUV-M MAX 144 segments (SEG36×COM4)
Datasheet
Command transfer method
Issue Slave Address (“01111100” for →rite Mode or “01111101” for Read Mode) after generate “START condition”.
1byte after Slave Address always becomes command input.
The least significant bit (LSB” of the Slave Address determines if the operation to be done is →rite or Read operation.
MSB (“command or data judge bit”) of command decide to next data is command or display data.
→hen set “command or data judge bit”=„1‟, next byte will be command.
→hen set “command or data judge bit”=„0‟, next byte data is display data.
S Slave address A 1 Command A 1 Command A 1 Command A 0 Command A Display Data … P
Once it becomes display data transfer condition, it cannot input command.
→hen want to input command again, please generate “START condition” once.
If “START condition” or “STOP condition” are inputted in the middle of command transmission, command will be
canceled.
If Slave address is continuously inputted following “START condition”, it will be in command input condition.
Please input “Slave Address” in the first data transmission after “START condition”.
When Slave Address cannot be recognized in the first data transmission, Acknowledge does not return and next
transmission will be invalid. →hen data transmission is in invalid status, if “START conditions” are transmitted again, it will
return to valid status.
Please consider the MPU interface characteristic such as Input rise time and Setup/Hold time when transferring
command and data (Refer to MPU Interface).
Write display and transfer method
Set R/→ bit to “0” to come into →rite Mode.
This device has Display Data RAM (DDRAM) of 36×4=144bit.
The relationship between data input and display data, DDRAM data and address are as follows;
Slave address
Command
Command
S 0111110 0 A 1 1101 000 A 0 0000000 _{A a b c d e f g h A i j k l m n o p A … P}
R/W=0 (Write Mode)
Display Data
8 bit data will be stored in DDRAM. The address to be written is the address specified by ADSET command, and the
address is automatically incremented in every 4bit data.
Data can be continuously written in DDRAM by transmitting Data continuously.
(When RAM data is written successively after writing RAM data to 23h (SEG35), the address is returned to 00h (SEG0)
by the auto-increment function.
DDRAM address
00 01 02 03 04 05 06 07
0a
e
i
m
1b
f
j
n
BIT _{2 c}
g
k
o
3d
h
l
p
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
・・・
21h 22h 23h
COM0
COM1
COM2
COM3
SEG33 SEG34 SEG35
Data transference to DDRAM will be executed in every 4bit data.
So it will be finished to transfer with no need to wait ACK.
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26.Aug.2013 Rev.001