BU2152FS_15 Datasheet, PDF (7/16 Pages) Rohm – 4-input Serial-in / Parallel-out Drivers

BU2152FS
Timing Chart
CLK
DATA
DATA24 DATA23 DATA22
DATA2 DATA1
STB
P1～P24
SO
Previous
DATA
Previous Previous
DATA24 DATA23
DATA
Previous
DATA2
Previous
DATA1
DATA24
DATA23
DATA22
Figure 5. Timing Chart
1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 24 data bits
into the DATA terminal.
2. P1 to P24 parallel output data of the shift register is set after the 24^th clock by the LCK.
3. Since the STB is a level trigger latch, data is retained in the “H” section and renewed in the “L” section of the
STB.
4. The final stage data of the shift register is outputted to the SO by synchronizing with the rise time of the CLK.
ï¼»Truth Tableï¼½
Input
CLK
STB
×
×
H
L
H
L
Function
CLB
All the data of the latch circuit are set to “H” (data of shift register does not
L
change), all the parallel outputs are “H”.
Serial data of DATA pin are latched to the shift register.
H
At this time, the data of the latch circuit does not change.
The data of the shift register are transferred to the latch circuit, and the data of
the latch circuit are outputted from the parallel output pin.
H
The data of the shift register shifts 1bit, and the data of the latch circuit and
parallel output also change.
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TSZ22111・15・001
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TSZ02201-0RHR1GZ00150-1-2
24.Aug.2015 Rev.002