BU2099FV_15 Datasheet, PDF(7/16 Page) Rohm – 4-input Serial-in / Parallel-out Drivers

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BU2099FV_15 Datasheet, PDF (7/16 Pages) Rohm – 4-input Serial-in / Parallel-out Drivers

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BU2099FV

Timing Chart

CLOCK

DATA

DATA12 DATA11 DATA10

DATA2 DATA1

LCK

âHâ

Previous DATA

Previous Previous

DATA11 DATA10

Figure 6 . Timing Chart

DATA

DATA12 DATA11

1. After the power is turned on and the voltage is stabilized, LCK should be activates, after clocking 12 data bits

into the DATA terminal.

2. Qx parallel output data of the shift register is set after the 12th clock by the LCK.

3. Since the LCK is a label latch, data is retained in the âLâ section and renewed in the âHâ section of the LCK.

4. Data retained in the internal latch circuit is output when the OE is in the âLâ section.

5. The final stage data of the shift register is output to the SO by synchronizing with the rise time of the CLOCK.

ï¼»Truth Tableï¼½

CLOCK

Input

DATA

LCK

Function

All the output data output âHâ with pull-up.

The Q0ï½Q11 output can be enable and output the data of storage register.

Store âLâ in the first stage data of shift register, the previous stage data in the

others. (The conditions of storage register and output have no change.)

Store âHâ in the first stage data of shift register, the previous stage data in

the others. (The conditions of storage register and output have no change.)

The data of shift register has no change.

SO outputs the final stage data of shift register with synchronized falling

edge of CLOCK, not controlled by OE.

The data of shift register is transferred to the storage register.

The data of storage register has no change.

(Note 2)The Q0ï½Q11 output have a Nch open drain FET . The FET is ON when data from shift register is âLâ, and the FET is OFF when data is âHâ.

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