BU2092F_15 Datasheet, PDF(7/17 Page) Rohm – 4-input Serial-in / Parallel-out Drivers

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BU2092F_15 Datasheet, PDF (7/17 Pages) Rohm – 4-input Serial-in / Parallel-out Drivers

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BU2092F BU2092FV

Timing Chart

CLOCK

DATA

DATA11 DATA10 DATA9

LCK

DATA1 DATA0

âHâ

Previous DATA

DATA11ï½0

(Note3) Diagram shows a status where a pull-up resistor is connected to output.

Figure 6 . Timing Chart

1. After the power is turned on and the voltage is stabilized, LCK should be activated, after clocking 12 data bits

into the DATA terminal.

2. Qx parallel output data of the shift register is set after the 12th clock by the LCK.

3. Since the LCK is a label latch, data is retained in the âLâ section and renewed in the âHâ section of the LCK.

4. Data retained in the internal latch circuit is output when the OE is in the âLâ section.

ï¼»Truth Tableï¼½

CLOCK

Input

DATA

LCK

Function

Output (Q0 to Q11) Disable

Output (Q0 to Q11) Enable

Store âLâ in the first stage data of shift register, the previous stage data in the

others. (The conditions of storage register and output have no change.)

Store âHâ in the first stage data of shift register, the previous stage data in the

others. (The conditions of storage register and output have no change.)

Ã The data of shift register has no change.

Ã The data of shift register is transferred to the storage register.

Ã The data of storage register has no change.

I/O Equivalence Circuits

DATA,CLOCK,LCK,OE

VDD

Q0 to Q11

DATA

CLOCK

LCK

VSS

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TSZ02201-0RHR1GZ00130-1-2

18.Sep.2015 Rev.002

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