BM67290FV-C Datasheet, PDF (7/33 Pages) Rohm – Built-in input PWM modulation circuit

BM67290FV-C
(4) Timing when VDD2 is tuned OFF before VDD1
When VDD2 reaches VthLVDD2, the outputs become SD1=H, SD2=L and OUT=L even if REF and CT are still
active.
VthVDD2
VDD2
0V
VthVDD1H
VthVDD1L
VDD1
0V
VthREFH
VthREFL
REF
0V
VthOV, VACT
VthOV×VOVZ
VHVACT
VthHPWML
( CT )
VH
VDTY
VthLV
VthLV×VLVH
VthLPWL
0V
H
( CLK )
L
VDD2
OUT
0V
H
( PRT1 )
L
H
( PRT2 )
L
VDD2
SD1
0V
Hi-Z
SD2
0V
Figure 6. VDD2 Stop to VDD1 Stop Timing Chart
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10.Nov.2014 Rev.001