BD9540EFV Datasheet, PDF (7/18 Pages) Rohm – 2ch Switching Regulators for Desktop PC

BD9540EFV
Technical Note
●Pin Descriptions
・EN1 (3 pin) / EN2 (12 pin)
When the input voltage on the EN pin reaches at least 2.2V, the switching regulator becomes active.
At voltages less than 0.3 V, the switching regulator becomes inactive, and the input current drops to 10μA or less.
Thus the IC can be controlled from 2.5V, 3.3V or 5V power supplies.
・5VReg (22 pin)
5.0V reference voltage output pin. If at least 2.2V is supplied to either the EN1 or EN2 pin, the reference output is switched on.
This pin supplies 5.0V at up to 10mA. Inserting a 4.7μF capacitor (with a X5R or X7R rating) between the 5VReg and GND
pins is recommended.
・ILIM1 (24 pin) / ILIM2 (19 pin)
The IC monitors the voltage between the SW pin and PGND pin as a control for the output current protection (OCP) mechanism.
The voltage at which OCP engages is determined by the resistance value connected to the ILIM pin.
This also allows for compatibility with FETs of various RON values.
・VIN (23 pin)
The IC determines the duty cycles internally based upon the input voltage on this pin. Therefore, variations in voltage on
this pin can lead to highly unstable operation. This pin also acts as the voltage input to the internal switching regulator
block, and is sensitive to the impedance of the power supply. Attaching a bypass capacitor or RC filter on this pin as
appropriate for the application is recommended.
・BOOT1 (1 pin) / BOOT2 (14 pin)
This pin supplies voltage used for driving the high-side FET. Maximum absolute ratings are 25V from GND and 5.5V from
SW. BOOT voltage swings between VIN + 5VReg and 5VReg during active operation.
・HG1 (28 pin) / HG2 (15 pin)
This pin supplies voltage used for driving the gate of the high-side FET. This voltage swings between BOOT and SW.
High-speed gate driving for the high side FET can be achieved due to its low on-resistance (5.5Ω when HG = high, 2.5Ω
when HG = low) of the driver.
・SW1 (27 pin) / SW2 (16 pin)
This pin acts as the source connection to the high-side FET. Maximum absolute rating is 20V from GND.
SW voltage swings between VIN and GND.
・LG1 (26 pin) / LG2 (17 pin)
This pin supplies voltage used for driving the gate of the low-side FET. This voltage swings between VDD and PGND.
High-speed gate driving for the low-side FET can be achieved due to its low on-resistance (4Ω when LG = high, 2Ω when
LG = low) of the driver.
・PGND1 (25 pin) / PGND2 (18 pin)
This pin acts as the ground connection to the source of the low-side FET.
・GND (7 pin)
This is the ground pin for all internal analog and digital power supplies.
・VOUT1 (4 pin) / VOUT2 (11 pin)
This is the output voltage sense pin; this pin features an integrated discharge FET used to discharge the output capacitor
when status is set to OFF.
・FB1 (5 pin) / FB2 (10 pin)
This is the output feedback pin. While the internal reference voltage of channel 2 is fixed at 0.750V, the internal reference
voltage of channel 1 is adjustable depending on the input conditions of the CTL1 and CTL2 pins.
・Vcc (21 pin)
This is the power supply pin for all internal circuitry. This pin can be supplied directly by a 5V source, or via an RC filter
(10 Ω, 0.01μF) from the 5VReg pin.
・CTL1 (8 pin) / CTL2 (9 pin)
These pins allow for the adjustment of the internal voltage reference (REF1) for channel 1. The pins recognize logic High
at VCC-0.5 V or above, and logic Low at 0.5 V or below. Refer to the voltage adjustment table for REF1 on page 12.
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2009.04 - Rev.B