BD9151MUV Datasheet, PDF (7/17 Pages) Rohm – Output 1.5A or Less High Efficiency Step-down Switching Regulator with Built-in Power MOSFET

BD9151MUV
Technical Note
●Description of operations
・Soft start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0µF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of BU9151MUV is supplied. And the hysteresis width of
100mV (Typ.) is provided to prevent output chattering. Each the outputs have UVLO. It is possible to set output sequence easy.
・Reset function
When AVCC input voltage is over .2.97V (typ), after 16msec (typ.) delay, outputs RESET. The hysteresis is 100mV (Typ).
・Pch MOSFET gate controller function
PGATEB pin has function to make FET active with steady current. With connecting Pch MOSFET gate, soft start turned to be ON.
・Discharge function
MONI pin is open drain pin of Nch MOS. After 4msec (typ) delay from the time UVLO release, it turns to be OFF.
By Low, UVLO detection of EN pin, Nch MOS becomes active and discharge the connection.
・External synchronous signal output function
PGATE pin outputs High active after 4msec (Typ.) delay from the UVLO release.
・Start up sequence function
BU9151MUV outputs output voltage 2ch (1.2V) after the UVLO release, and after 2msec(typ.) from the UVLO release,
it outputs 1ch(1.8V), and the last, after 4msec from the UVLO release, PGATEB becomes active, and external
Pch MOSFET will be ON, and outputs 3ch(VCC equivalent). During the OFF time, 3ch output is discharged by MONI pin,
then 1ch output and 2ch output are naturally discharged.
VUVLOH(2.6V)
VUVLOL(2.5V)
VCC
PG2 (2.97V)
PG1 (2.87V)
EN
VOUT1(1.8V)
VOUT2(1.2V)
PGATE
PGATEB
T SS (0.5m s)
T S S(0.5m s)
delay1 (2ms)
delay2 (4ms)
VOUT3(3.3V)
RESET
T SS (1m s)＊
TPG (16ms)
TSS
TSS
delay1 (2ms)
delay2 (4ms)
discharge ON
T SS (1m s)＊
TPG (16ms)
discharge ON
TSS
TSS
delay1 (2ms)
delay2 (4ms)
T SS (1m s)＊
TPG (16ms)
discharge ON
*Starting time of VOUT3 TSS=1ms (when BD9151MUV is used) It depends on gate capacity when using Pch MOSFET
Fig.30 Soft start, Shut down, UVLO timing chart
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2009.08 - Rev.A