BU2050F_16 Datasheet, PDF (6/15 Pages) Rohm – 4-input Serial-in / Parallel-out Drivers

BU2050F
Timing chart
CLK
DATA ^{DATA8 DATA7 DATA6}
DATA2 DATA1
CLR
STB
P1 to P8
Previous DATA
DATA
“L”
Figure 7. Timing chart
1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into
the DATA pin.
2. Parallel outputs (P1 to P8) are set to the shift register data after the eighth clock by the STB.
3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB.
ï¼»Function Explanationï¼½
・ A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch
circuit is reset non-synchronously without the other input condition, and all parallel outputs change into “L”.
・ A serial data inputted from DATA terminal is read in shift register with synchronized rising transition of clock.
In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and
outputs from the parallel data output terminal (P1 to P8). In case of STB is “H”, all parallel outputs and the
data of latch do not change.
ï¼»Truth Tableï¼½
Input
CLK
STB
×
×
H
L
H
L
CLR
L
H
H
Function
All the data of the latch circuit are set to “L” (data of shift register does not
change), all the parallel outputs are “L”.
Serial data of DATA pin are latched to the shift register.
At this time, the data of the latch circuit does not change.
The data of the shift register are transferred to the latch circuit, and the data of
the latch circuit are outputted from the parallel output pin.
The data of the shift register shifts 1bit, and the data of the latch circuit and
parallel output also change.
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TSZ22111・15・001
6/11
TSZ02201-0RHR1GZ00120-1-2
18.Apr.2016 Rev.003