BU8255KVT Datasheet, PDF (5/17 Pages) Rohm – 35bit LVDS Receiver 5:35 DeSerializer

●Pin Description
Table .1: Pin description
Pin Name Pin No.
RA+, RA-
50,49
RB+, RB-
52,51
RC+, RC-
55,54
RD+, RD-
60,59
RE+, RE-
RCLK+,
RCLK-
RA6～RA0
RB6～RB0
RC6～RC0
RD6～RD0
RE6～RE0
RESERVE
62,61
57,56
40,41,42,43,
45,46,47
32,33,34,35,
36,38,39
22,24,25,26,
27,28,29
14,15,17,18,
19,20,21
6,7,8,10,11,1
2,13
2
PD
3
OE
4
R/F
5
VDD
CLKOUT
GND
LVDD
LGND
PVDD
PGND
9,23,37,48
31
1,16,30,44
53
58
64
63
I/O
LVDS Input
LVDS Input
LVDS Input
LVDS Input
LVDS Input
LVDS Input
Output
Output
Output
Output
Output
Input
Input
Input
Input
Power
Output
Ground
Power
Ground
Power
Ground
Description
LVDS data input
+ : Positive input of LVDS data differential pair.
- : Negative input of LVDS data differential pair.
LVDS clock input
LVCMOS data outputs.
Reserved input, must be “Low” for normal operation.
Power down input for the internal system.
H: Normal operation.
L: Power down (All output are “Low”).
Power down input for the data output driver.
H: Output enable (Normal operation).
L: Output disable(All outputs are “Hi-Z”).
Select input pin for data output clock triggering edge.
H: Output data is latched on rising edge.
L: Output data is latched on falling edge.
3.3V output driver and digital core power supply pin.
LVCMOS level clock output.
GND pin for both data output driver cells and the digital
cores.
Power supply pin for LVDS inputs.
Ground pin for LVDS inputs.
Power supply pin for PLL core.
Ground pin for PLL core.
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