BU42XXG_09 Datasheet, PDF (5/12 Pages) Rohm – Low Voltage Free Delay Time Setting CMOS Voltage Detector IC Series

BU42□□G series, BU42□□F series, BU42□□FVE series,
BU43□□G series, BU43□□F series, BU43□□FVE series
Technical Note
●Setting of Detector Delay Time
This detector IC can be set delay time at the rise of VDD by the capacitor connected to CT terminal.
Delay time at the rise of V_DD T_PLH:Time until when Vout rise to 1/2 of V_DD after V_DD rise up and beyond the release
voltage(V_DET+∆V_DET)
C_CT:
R_CT:
T_PLH=-1×C_CT×R_CT×ln
V_DD-V_CTH
V_DD
CT pin Externally Attached Capacitance
CT pin Internal Impedance(P.2 R_CT refer.) Ln:
V_CTH:
CT pin Threshold Voltage(P.2 VCTH refer.)
Natural Logarithm
●Reference Data of Falling Time (T_PHL) Output
Examples of Falling Time (T_PHL) Output
Part Number
T_PHL [µs]
BU4245G
275.7
BU4345G
359.3
* This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
●Explanation of Operation
For both the open drain type(Fig.15)and the CMOS output type(Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the Vdd pins reaches the applicable threshold voltage, the Vout terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. BU42□□G/F/FVE and BU43□□G/F/FVE have delay
time function which set TPLH (Output “Low””High”) using an external capacitor (CCT). Because the BU42□□G/F/FVE
series uses an open drain output type, it is possible to connect a pull-up resistor to VDD or another power supply [The
output “High” voltage (VOUT) in this case becomes VDD or the voltage of the other power supply].
VDD
R1
Vref
R2
Q3
R3
GND
VDD
VOUT
RESET
Q1
CT
Fig.15 (BU42□□ type internal block diagram)
VDD
GND
R1
Vref
R2
R3
VDD
Q3
Q2
RESET
VOUT
Q1
CT
Fig.16 (BU43□□ type internal block diagram)
●Timing Waveforms
Example: the following shows the relationship between the input voltage VDD, the CT Terminal Voltage VCT and the output
voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in
Fig.15 and 16).
① When the power supply is turned on, the output is unsettled from
after over the operating limit voltage (VOPL) until TPHL. There fore it is
VDET+ΔVDET
VDET
VDD
VOPL
0V
⑤
possible that the reset signal is not outputted when the rise time of
VDD is faster than TPHL.
② When VDD is greater than VOPL but less than the reset release
voltage (VDET+∆VDET), the CT terminal (VCT) and output (VOUT)
VCT
1/2 VDD
voltages will switch to L.
③ If VDD exceeds the reset release voltage (VDET+VDET), then VOUT
switches from L to H (with a delay to the CT terminal).
④ If VDD drops below the detection voltage (VDET) when the power
VOUT
TPHL
TPLH
TPHL
TPLH
supply is powered down or when there is a power supply fluctuation,
VOUT switches to L (with a delay of TPHL).
⑤ The potential difference between the detection voltage and the
①② ③ ④
Fig.17
release voltage is known as the hysteresis width (VDET). The system
is designed such that the output does not flip-flop with power supply
fluctuations within this hysteresis width, preventing malfunctions due
to noise.
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5/11
2009.11 - Rev.C