BR93G86-3 Datasheet, PDF (5/39 Pages) Rohm – Serial EEPROM series Standard EEPROM MicroWire BUS EEPROM (3-Wire)

BR93G86-3
●Serial input / output timing
Datasheet
CS
t _{CS S}
SK
t _DIS
DI
DO (READ)
t _SV
DO(WRITE )
1 / f_SK
t _{S KH}
t_SKL
t_{D IH}
t_{P D0}
t_PD1
STATUS VALID
t_CSH
t _DF
Figure 1. Sync data input / output timing
○Data is taken by DI sync with the rise of SK.
○At read operation, data is output from DO in sync with the rise of SK.
○The STATUS signal at write (READY / BUSY) is output after t_CS from the fall of CS after write command input, at the area
DO where CS is high, and valid until the next command start bit is input. And, while CS is low, DO becomes High-Z.
○After completion of each mode execution, set CS low once for internal circuit reset, and execute the following operation
mode.
○1/f_SK is the SK clock cycle, even if f_SK is maximum, the SK clock cycle can’t be t_SKH(Min.)+t_SKL(Min.)
○For “Write cycle time t_E/W”, please see Figure 36,37,39,40.
○For “CS low time t_CS”, please see Figure 36,37,39,40.
●Block diagram
CS
Command decode
Control
SK
Clock generation
DI
ORG
DO
Command
register
Dummy bit
Power source voltage detection
Write
prohibition
High voltage occurrence
Address
buffer
10bit or 11bit
Address
decoder
10bit or 11bit
Data
register
16bit/8bit
R/W
amplifier
16bit/8bit
16,384 bit
EEPROM
Figure 2. Block diagram
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21.JAN.2013 REV.001