BR25H128F-2LB_14 Datasheet, PDF (5/32 Pages) Rohm – Operation SPI BUS EEPROM

BR25H128F-2LB
Datasheet
Serial Input / Output Timing
CSB
SCK
tCS
tSCKS
tCSS
tSCKWL tSCKWH
tDIS tDIH
tRC
tFC
SI
SO
High-Z
Figure 2. Input timing
SI is taken into IC inside in sync with data rise edge of SCK. Input address and data from the most significant bit MSB.
tCS
CSB
tCSH ^tSCKH
SCK
SI
tPD
tOH
SO
tRO,tFO tOZ
High-Z
Figure 3. Input / Output timing
SO is output in sync with data fall edge of SCK. Data is output from the most significant bit MSB.
"H"
CSB
"L"
SCK
tHFS tHFH
SI
n+1
SO
Dn+1
tHOZ
Dn
tHRS tHRH
High-Z
tDIS
n
tHPD
Dn
n-1
Dn-1
HOLDB
Block diagram
CSB
SCK
SI
HOLDB
WPB
SO
Figure 4. HOLD timing
INSTRUCTION DECODE
CONTROL CLOCK
GENERATION
VOLTAGE
DETECTION
WRITE
INHIBITION
HIGH VOLTAGE
GENERATOR
INSTRUCTION
REGISTER
ADDRESS
14bit
REGISTER
DATA
8bit
REGISTER
STATUS REGISTER
ADDRESS
14bit
DECODER
READ/WRITE
8bit
AMP
128K
EEPROM
Figure 5. Block diagram
www.rohm.com
©2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
5/28
TSZ02201-0R1R0G100370-1-2
27.Feb.2014 Rev.002